1. Technical Field
The present invention relates, in general, to an electronic package for interconnecting a semiconductor chip to a printed circuit board, and in particular, to an organic multi-layered interconnect structure that includes a high density interconnect layer such as an allayed surface layer.
2. Related Art
Organic substrates, such as chip carriers, have been and continue to be developed for many applications. Organic substrates are expected to displace ceramic substrates in many chip carrier applications because of reduced cost and enhanced electrical performance. An organic substrate, such as an organic chip carrier for interconnecting a semiconductor chip to a printed circuit board in an electronic package, may have a surface redistribution layer for redistributing electrical signals from the chip into a larger area so that the chip can properly interface with the printed circuit board.
As semiconductor chip input/output (I/O) counts increase beyond the capability of peripheral lead devices and as the need for both semiconductor chip and printed circuit board miniaturization increases, area array interconnects will be the preferred method for making large numbers of connections between a semiconductor chip and an organic chip carrier, and between the organic chip carrier and a printed circuit board. If the coefficient of thermal expansion (CTE) of the semiconductor chip, the organic chip carrier, and the printed circuit board are substantially different from one another, industry standard semiconductor chip array interconnections to the organic chip carrier may be subject to high stress during thermal cycling operation. Similarly, the industry standard ball grid array (BGA) interconnections between the organic chip carrier and printed circuit board may also be subject to high stress during operation. Significant reliability concerns may then become manifest by failure of the connections or even failure of the integrity of the semiconductor chip (chip cracking). These reliability concerns significantly inhibit design flexibility. For example, semiconductor chip sizes may be limited or interconnect sizes, shapes and spacing may have to be customized beyond industry standards to reduce these stresses. These limitations may limit the electrical performance advantages of the organic electronic package or add significant cost to the electronic package. Typically, a semiconductor chip has a CTE of 2-3 parts per million per degree Celsius (ppm/xc2x0 C.) while a standard printed circuit board has a much greater CTE of 17-20 ppm/xc2x0 C.
A particular reliability concern is that the surface redistribution layer, which interfaces between the organic substrate and the semiconductor chip, may be susceptible to stresses resulting from thermal cycling of the organic substrate together with a chip solderably coupled with the organic substrate. Such stresses result from a CTE differential between the surface redistribution layer and the remainder of the organic substrate. The ability of the surface redistribution layer to withstand such stresses depends on mechanical properties of the surface redistribution layer. If the redistribution layer cannot accommodate the thermal stresses, then the surface redistribution layer is susceptible to deterioration, such as cracking, which can cause failure of interconnections between the organic chip carrier and semiconductor chip, as well as between the organic chip carrier and printed circuit board. Thus, it is desirable for the surface redistribution layer to include a material having thermal and mechanical properties that enable the redistribution layer to reliably retain its structural integrity during thermal cycling operations.
The present invention provides a multi-layered interconnect structure, comprising:
a thermally conductive layer including first and second opposing surfaces;
a first and a second dielectric layer positioned on the first and the second opposing surfaces, respectively, of the thermally conductive layer;
first and second pluralities of electrically conductive members positioned on said first and second dielectric layers, respectively;
a first electrically conductive layer within said first dielectric layer;
a second electrically conductive layer within said first dielectric layer and positioned between said first electrically conductive layer and said thermally conductive layer, wherein said second electrically conductive layer comprises a first plurality of shielded signal conductors;
a plated through hole through the multi-layered interconnect structure electrically connected to at least one member of said first plurality of electrically conductive members, to at least one of said first plurality of shielded signal conductors, and to at least one member of said second plurality of electrically conductive members; and
a third dielectric layer positioned on said first dielectric layer and on portions of said first plurality of electrically conductive members, said third dielectric layer substantially overlying said plated through hole, and wherein said third dielectric layer includes a first high density interconnect layer for providing an electrical path from a first electronic device to the first plurality of shielded signal conductors.
The present invention provides a method of making a multi-layered interconnect structure, comprising the steps of:
providing a thermally conductive layer including first and second opposing surfaces;
forming first and second dielectric layers on said first and second opposing surfaces, respectively, of said thermally conductive layer;
forming first and second pluralities of electrically conductive members on said first and second dielectric layers, respectively;
forming a first electrically conductive layer within said first dielectric layer;
forming a second electrically conductive layer within said first dielectric layer and positioned between said first electrically conductive layer and said thermally conductive layer, wherein said second electrically conductive layer comprises a first plurality of shielded signal conductors;
forming a plated through hole through the multi-layered interconnect structure electrically connected to at least one member of said first plurality of electrically conductive members, to at least one of said first plurality of shielded signal conductors, and to at least one member of said second plurality of electrically conductive members; and
forming a third dielectric layer on said first dielectric layer and on portions of said first plurality of electrically conductive members, said third dielectric layer substantially overlying said plated through hole, and wherein said third dielectric layer includes first high density interconnect layer for providing an electrical path from a first electronic device to the first plurality of shielded signal conductors.
The present invention has the advantage of using a material in the surface redistribution layer that reliably retains its structural integrity during thermal cycling operations and, in particular, satisfies the stringent standards of Thermal Acceptance Testing (TAT), to be described infra.
The present invention has the advantage of having a high density interconnect layer for providing a direct electrical path from the multi-layered interconnect structure to an external electronic device.
The present invention has the advantage of using a material in the surface high density interconnect layer that does not include a substance capable of vaporizing during thermal cycling, wherein such vaporization would cause shrinkage of the redistribution layer.
The present invention has the advantage of providing a high density interconnect layer having an exposed surface that is intrinsically rough. Since the surface roughness facilitates subsequent deposition of conductive metal on the surface, additional process steps to purposefully create surface roughness are avoided.